1. Field of the Invention
The present invention relates to a method of determining reliability of semiconductor products, and more particularly, to a method of determining negative bias temperature instability (NBTI) of PMOS transistors.
2. Description of the Prior Art
Negative bias temperature instability (NBTI) becomes increasingly serious as device dimensions are continually scaled down. It has been reported by N. Kimizuka et al. (VLSI Tech., p.73, 1999) that threshold voltage shift (xcex94Vth) of PMOS transistors due to NBTI degradation mode starts to limit device lifetime when oxide thickness is less than 3.5 nm.
Although much effort has been recently dedicated to the study of NBTI, the details of the degradation process are not well understood. Therefore, a common method of determining NBTI is by directly stressing samples through package level or wafer level at a high bias and a high temperature for a long period of time, which is at least 105 seconds. Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art method of determining reliability of a semiconductor device. As shown in FIG. 1, a PMOS transistor 10 is formed on an N-type substrate 12 of a semiconductor wafer. The prior art method includes placing the semiconductor wafer in a high temperature environment and stressing the gate 16 of the PMOS transistor 10 with a high bias 14. During a testing time period, the threshold voltage of the PMOS transistor is measured and a threshold voltage shift is calculated by operating with the initial threshold voltage of the PMOS transistor before stressing. Furthermore, reliability of the semiconductor device is evaluated.
The prior art method requires at least 105 seconds for measuring the threshold voltage shift of the semiconductor device under a condition of high bias and high temperature. Therefore, the prior determining method must be operated by hand and consumes a lot of time, which results in an increase of product costs.
It is therefore a primary objective of the claimed invention to provide a method of determining reliability of semiconductor products for solving the above-mentioned problems.
According to the claimed invention, a method of determining reliability of semiconductor products is provided. The method comprises providing a semiconductor wafer, which comprises a plurality of MOS transistors formed on its surface, and placing the semiconductor wafer in an environment of a stress temperature during a testing time period. The MOS transistor is simultaneously stressed with a stress voltage. A plurality of testing points are defined in the testing time, and the threshold voltage shift of the MOS transistor is measured at each testing point for establishing a group of experimental data. Finally, a relationship model of threshold voltage shift (xcex94Vth) vs. time (t) is provided, and the group of experimental data and the relationship model are used to depict a relation curve for predicting the threshold voltage shift of the MOS transistor when exceeding the testing time.
It is an advantage over the prior art that the determining method of the claimed invention uses a group of experimental data and a relationship model to depict a curve for predicting threshold voltage shift of a semiconductor device. Therefore, the semiconductor device only needs to be stressed and measured for a short time for depicting a relation curve, which predicts threshold voltage shift of the device during a longer time period. Manpower and time costs of the semiconductor products are thereby effectively reduced.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.